//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths


module AURG_FIFO_RAM18K_9_9(
   input                      CLKA,
   input                      WEA,
   input[10:0]                ADDRA,
   input[8:0]                 DINA,

   input                      CLKB,
   input[10:0]                ADDRB,
   output[8:0]                DOUTB
   );


AUPP_XLNX_RAM18K_9_9         INST_RAM18K_9_9(
   .clka                     ( CLKA ),
   .wea                      ( WEA ),
   .addra                    ( ADDRA[10:0] ),
   .dina                     ( DINA[8:0] ),
   .clkb                     ( CLKB ),
   .addrb                    ( ADDRB[10:0] ),
   .doutb                    ( DOUTB[8:0])
   );


endmodule
